How does hardware design language set up logic gates on an FPGA?

Hardware Description Languages (HDLs) like Verilog and VHDL configure FPGAs by describing digital circuits that are then synthesized, placed, and routed onto the FPGA fabric. Here's the complete process:

1. HDL Code Describes Behavior

Basic Gate-Level Description (Verilog):

verilog

// AND gate description
module and_gate(
    input wire a,
    input wire b, 
    output wire y
);
    assign y = a & b;
endmodule

// More complex example
module simple_alu(
    input wire [3:0] a, b,
    input wire [1:0] op,
    output reg [3:0] result
);
    always @(*) begin
        case(op)
            2'b00: result = a + b;      // Adder
            2'b01: result = a & b;      // AND gate
            2'b10: result = a | b;      // OR gate  
            2'b11: result = ~a;         // NOT gate
        endcase
    end
endmodule

2. The FPGA Compilation Flow

Step-by-Step Process:

text

HDL Code → Synthesis → Technology Mapping → Placement → Routing → Bitstream

3. Synthesis: HDL to Generic Gates

The synthesis tool converts HDL into a gate-level netlist:

Original HDL:

verilog

module logic_function(
    input wire a, b, c,
    output wire y
);
    assign y = (a & b) | c;
endmodule

After Synthesis (Generic Gates):

text

AND2 gate1(.a(a), .b(b), .out(n1))
OR2  gate2(.a(n1), .b(c), .out(y))

4. Technology Mapping to FPGA Primitives

FPGAs don't have discrete gates—they use Look-Up Tables (LUTs):

LUT Implementation:

• A LUT is a small memory that implements any logic function

• Most FPGAs use 4-input, 6-input, or 8-input LUTs

Example: Our logic function y = (a & b) | c mapped to a 3-input LUT:

The LUT is programmed with these values to implement the exact truth table.

5. FPGA Architecture Components

Basic FPGA Building Blocks:

text

CLB (Configurable Logic Block)
├── LUTs (Look-Up Tables) - implements logic
├── Flip-Flops - for registers
└── Multiplexers - for routing

+ Interconnect Network (programmable wires)
+ I/O Blocks (programmable I/O pins)
+ Specialized Blocks (RAM, DSP, etc.)

6. Placement and Routing

Placement:

The tool decides where each LUT goes on the FPGA grid.

Routing:

The tool programs the switch matrices to connect LUTs together:

verilog

// This HDL...
module adder(
    input wire [3:0] a, b,
    output wire [3:0] sum
);
    assign sum = a + b;
endmodule

// Becomes placed and routed as:
LUT4 at location X10Y15 → implements bit 0 of adder
LUT4 at location X10Y16 → implements bit 1 of adder  
LUT4 at location X11Y15 → implements bit 2 of adder
LUT4 at location X11Y16 → implements bit 3 of adder

// With programmable switches connecting them

7. Complete Example: 4-bit Counter

HDL Code:

verilog

module counter_4bit(
    input wire clk,
    input wire reset,
    output reg [3:0] count
);
    always @(posedge clk or posedge reset) begin
        if (reset)
            count <= 4'b0000;
        else
            count <= count + 1;
    end
endmodule

FPGA Implementation:

• 4 LUTs: Each implements 1 bit of the adder (count + 1)

• 4 Flip-Flops: Store the current count value

• 1 Global Clock Network: Distributes the clock signal

• Routing: Connects LUTs to flip-flops and between bits

8. Advanced HDL Constructs and Their Implementation

Case Statements → Multiplexers:

verilog

case(sel)
    2'b00: out = a;
    2'b01: out = b;
    2'b10: out = c;
    2'b11: out = d;
endcase

Implementation: One 4-input LUT per bit, configured as a 4:1 mux.

Arithmetic Operations → DSP Slices:

verilog

output reg [7:0] result = a * b;

Implementation: Uses dedicated DSP blocks instead of LUTs for efficiency.

Memory → Block RAM:

verilog

reg [7:0] memory [0:255];

Implementation: Uses dedicated Block RAM resources.

9. Timing and Constraints

Clock Constraints:

tcl

# SDC file tells the tools about timing requirements
create_clock -name clk -period 10 [get_ports clk]

# Result: Tools ensure all paths meet timing
# Setup time: Data arrives before clock edge
# Hold time: Data remains stable after clock edge

10. The Final Bitstream

The placement and routing information is converted into a bitstream that programs the FPGA:

Bitstream Contents:

• LUT Configuration: Truth table values for each LUT

• Routing Configuration: Switch matrix settings

• I/O Configuration: Pin directions and standards

• Clock Configuration: PLL and clock network settings

11. Real-World Design Flow

Typical FPGA Toolchain:

bash

# 1. Write HDL
code my_design.v

# 2. Synthesize
vivado -mode synth -top my_design

# 3. Implement (place & route)
vivado -mode impl -top my_design

# 4. Generate bitstream
vivado -mode bitgen -top my_design

# 5. Program FPGA
vivado -mode prog -bitfile my_design.bit

12. Key Concepts Summary

1. HDL describes behavior, not specific gates

2. Synthesis converts HDL to generic logic gates

3. Technology mapping converts gates to LUTs

4. Placement decides where LUTs go on the FPGA

5. Routing programs the interconnect between LUTs

6. Bitstream contains all configuration data

7. FPGA is reprogrammed on power-up with the bitstream

The magic is that the same FPGA fabric can implement any digital circuit by simply loading a different bitstream—this is what makes FPGAs so powerful for prototyping and flexible hardware implementation.